Field-effect transistors (“FETs”) are used in memory structures such as dynamic random access memories (“DRAMs”) for controlling access to capacitors used to store charge representing information contained in the memories. In DRAMs, charge leakage effects necessitate periodic refreshing of the information stored in the memory. In turn, refreshing of the DRAM leads to increased power consumption and delays in memory operation. Accordingly, it is desirable to reduce charge leakage effects in DRAMs.
Additionally, it is desirable to minimize the area required for fabrication of the elements of memories such as DRAMs. Electrical isolation of various circuit elements from each other is required. In turn, electrical isolation requires some of the space used on the DRAM or other integrated circuitry. Various techniques have been developed to reduce the amount of area needed for electrical isolation structures. One technique for providing a high degree of electrical isolation while requiring relatively little space is known as shallow trench isolation.
One source of charge leakage in DRAMs is related to carrier generation-recombination phenomena. In general, lower dopant concentrations tend to reduce this source of charge leakage. However, other concerns tend to determine lower bounds for dopant concentrations.
The FETs used as access transistors determine some of these other concerns. The FETs need to be able to provide a high impedance when they are turned OFF, and a low impedance connection when they are turned ON. DRAMs and other memories use an addressing scheme whereby a wordline that is coupled to many transistor gates is selected, and at the same time a bitline or digitline that is coupled to many transistor drains is also selected. A FET that is located at the intersection of the selected wordline and the selected bitline is turned ON, and that memory cell is accessed. At the same time, many other FETs have a drain voltage due to the drains of these FETs being coupled to the selected bitline. These FETs exhibit some parasitic conductance as a result of the drain voltage. In some types of integrated circuits, a portion of that parasitic conductance is due to corner effects that are an artifact of using trench isolation techniques to isolate the FETs from one another and from other circuit elements.
These effects are described in “Subbreakdown Drain Leakage Current in MOSFET” by J. Chen et al., IEEE El. Dev. Lett., Vol. EDL-8, No. 11, November 1987; “Impact Of Shallow Trench Isolation On Reliability Of Buried- And Surface-Channel Sub-μm PFET” by W. Tonti and R. Bolam, IEEE Cat. No. 0-7803-2031, 1995; “Shallow Trench Isolation For Advanced ULSI CMOS Technologies”, M. Nandakumar et al.; and “Shallow Trench Isolation Characteristics With High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide For Deep-Submicron CMOS Technologies”, S.-H. Lee et al., Jpn. J. Appl. Phys., Vol. 37, 1998, pp. 1222-1227, which publications are hereby incorporated herein by reference for their general background teachings.
One method of reducing these parasitic conduction effects is to round the corner where the isolation trench meets the surface of the semiconductor material. This may be effected by oxidizing the surface of the silicon, as is described in the above-noted publications. However, this approach requires additional processing steps, which tend to result in reduced yield, among other things.
What is needed is a way to incorporate trench isolation together with FETs that does not increase processing complexity and that provides compact, low-leakage transistors in DRAMs and other circuitry.